How Wissda can help you?
Minimum 5-8 years of solid experience in SoC design, with experience managing large teams
Good knowledge of Digital Design and RTL development
Hands-on experience with SoC Design, Verilog RTL coding
Create/ work on designs using Power domain & Low Power Design techniques.
Hands on in Clock Domain Crossing (CDC) checks, Linting, equivalence checks and Synthesis
Understanding of Bus protocols (AHB/AXI etc, interconnects, peripherals, DDR, clock & resets
Understanding of Memory controller designs and Microprocessors is desirable
Be an individual contributor in design Tasks Architecting ASIC designs, micro-architecting, RTL coding of design, debug etc.
Understanding of Chip IO design and packaging is desirable
Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification
Manage IP dependencies, planning and tracking of all front end design related tasks
Driving the project milestones across the design, verification and physical implementations
Experience in managing a team of talented engineers
Needs to make effective and timely decisions, even with incomplete information.
Provides direction, mentoring, and leadership to small to medium sized groups.
Should possess effective communication and leadership skills
Good people management, team work skills and strong positive attitude are essential
Understanding of System Verilog based verification
Experience with FPGA realizations of higher complexity designs
Experience of synthesis and back-end flows and tools
Experience in Low power design
B.E/B.Tech in Electronics