How Wissda can help you?
Strong verification skills, UVM methodology
Object oriented programming, white-box/black-box, directed/random testing, coverage.
Strong capability in building a verification environment
Scripting Perl/ Python/Shell
Design verification Skills
Miscellaneous tasks in connection to the block design
Verification environment (creation/adaptation/maintenance).
Test case creation
Usage of reference models
Constrained random testing
Creation of Coverage matrix
5-8 years of experience in verification
Good experience in System Verilog and UVM Methodology based verification
Excellent experience in module level & SoC level verification
Experience in verifying ARM based designs
B.E/B.Tech in Electronics