Sr Verification Engineer

Full Time
APAC Region
Posted 2 years ago

Required Skills:
Strong verification skills, UVM methodology

Object oriented programming, white-box/black-box, directed/random testing, coverage.

Strong capability in building a verification environment

Scripting Perl/ Python/Shell

Design verification Skills

Miscellaneous tasks in connection to the block design

Verification planning

Verification specification

Verification environment (creation/adaptation/maintenance).

Verification documentation

Test case creation

Usage of reference models

Constrained random testing

Creation of Coverage matrix

Experience
5-8 years of experience in verification

Good experience in System Verilog and UVM Methodology based verification

Excellent experience in module level & SoC level verification

Experience in verifying ARM based designs

Min. Qualification
B.E/B.Tech in Electronics

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